A semiconductor (IC) has a large number of circuit devices with complex interconnections. The placement and interconnection of the components of the IC may be facilitated with an Electronic Design Automation (EDA) tool, which allows flexibility in design and optimization of the IC. EDA technologies typically run on an operating system in conjunction with a microprocessor-based computer system or other programmable control system.
One of the challenges for an IC circuit is to construct a clock-distribution tree that carries clock-signal to the synchronous circuit devices in the IC without significant clock-skews or clock-latencies. In other words, the challenge is to construct a clock-distribution tree, wherein all of the unevenly distributed clock sinks in the IC have same or nearly the same wirelength from the clock-signal source. A clock sink may be a synchronous circuit device such as a flip-flop or may be a clock buffer connected to one or more synchronous circuit devices. In addition to the complexity of uneven distribution of the clock-sinks, there may be an additional layer of complexity of various routing and/or placement blockages within the IC that limit the potential locations for construction of a clock-distribution tree.
For example, a clock-tree distribution network may be constructed at higher layers of the IC, where the metal pitch of the interconnecting wires is substantially greater than those of the lower layers. Therefore, the wires at higher layers of the IC require thicker routing channels occupying a larger surface area. The required large surface area may not readily available because of the large number of components placed on the IC. Furthermore, the power grid or the power mesh for the IC may in the same layer as the clock layer. The presence of power grid may create more routing and/or blockages further complicating the construction of a symmetric clock-distribution tree with a minimal amount of clock-skew.
Conventional methods construct a clock-distribution tree by placing an entire clock-tree structure on the IC without the placement and routing blockage considerations. In the conventional methods, a clock-tree is placed centered around the middle portion of the IC. When a clock-signal wire of the tree encounters a routing blockage, the conventional methods simply route the clock-signal wire around the blockage. Each of the clock-signal wires may encounter an unique routing blockage and, therefore, each of the clock-signal wires may have to be routed differently by the conventional methods, such as detouring at the same layer or routing at a lower layer. The conventional methods further do not consider the effect of routing a clock-signal wire to the other clock-signal wires in the clock-distribution tree. The end result of the conventional methods is a non-symmetric, a high-skew, and less efficient clock distribution tree, which cannot be used for high performance and fast ICs.